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FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
15 years 4 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
ICPP
2008
IEEE
15 years 4 months ago
Scalable Dynamic Load Balancing Using UPC
An asynchronous work-stealing implementation of dynamic load balance is implemented using Unified Parallel C (UPC) and evaluated using the Unbalanced Tree Search (UTS) benchmark ...
Stephen Olivier, Jan Prins
IEEEPACT
2008
IEEE
15 years 4 months ago
Exploiting loop-dependent stream reuse for stream processors
The memory access limits the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip storage, the number of memory acc...
Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers,...
NOMS
2008
IEEE
15 years 4 months ago
A novel approach to bottleneck analysis in networks
—In this paper∗ , we devise a novel method for bottleneck analysis of UDP networks based on the concept of network utility maximization. To determine the losses on the links in...
Nikhil Shetty, Assane Gueye, Jean C. Walrand
WCRE
2008
IEEE
15 years 4 months ago
Reverse Engineering CAPTCHAs
CAPTCHAs are automated Turing tests used to determine if the end-user is human and not an automated program. Users are asked to read and answer Visual CAPTCHAs, which often appear...
Abram Hindle, Michael W. Godfrey, Richard C. Holt