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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
15 years 2 months ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas
PLDI
2010
ACM
15 years 2 months ago
Mixing type checking and symbolic execution
Static analysis designers must carefully balance precision and efficiency. In our experience, many static analysis tools are built around an elegant, core algorithm, but that alg...
Yit Phang Khoo, Bor-Yuh Evan Chang, Jeffrey S. Fos...
ICS
2001
Tsinghua U.
15 years 2 months ago
Cache performance for multimedia applications
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
Nathan T. Slingerland, Alan Jay Smith
ISCOPE
1999
Springer
15 years 1 months ago
Using Object-Oriented Techniques for Realizing Parallel Architectural Skeletons
The concept of design patterns has recently emerged as a new paradigm in the context of object-oriented design methodology. Similar ideas are being explored in other areas of compu...
Dhrubajyoti Goswami, Ajit Singh, Bruno R. Preiss