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NOCS
2008
IEEE
15 years 4 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
103
Voted
ACMMSP
2006
ACM
260views Hardware» more  ACMMSP 2006»
15 years 3 months ago
Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
Michael D. Adams, David S. Wise
ASPLOS
2006
ACM
15 years 3 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
89
Voted
CASES
2006
ACM
15 years 3 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
W4A
2006
ACM
15 years 3 months ago
Transforming web pages to become standard-compliant through reverse engineering
Developing Web pages following established standards can make the information more accessible, their rendering more efficient, and their processing by computer applications easier...
Benfeng Chen, Vincent Y. Shen