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DATE
2010
IEEE
162views Hardware» more  DATE 2010»
15 years 9 months ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
15 years 9 months ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
15 years 9 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
ICSM
2002
IEEE
15 years 9 months ago
Static and Dynamic C++ Code Analysis for the Recovery of the Object Diagram
When a software system enters the maintenance phase, the availability of accurate and consistent information about its organization can help alleviate the difficulties of program...
Paolo Tonella, Alessandra Potrich
ISPAN
2002
IEEE
15 years 9 months ago
On the Impact of Naming Methods for Heap-Oriented Pointers in C Programs
Many applications written in C allocate memory blocks for their major data structures from the heap space at runtime. The analysis of heap-oriented pointers in such programs is cr...
Tong Chen, Jin Lin, Wei-Chung Hsu, Pen-Chung Yew