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IPPS
2006
IEEE
15 years 10 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
ISCAS
2006
IEEE
78views Hardware» more  ISCAS 2006»
15 years 10 months ago
A low power SoC bus with low-leakage and low-swing technique
Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 10 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...