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2005
IEEE
99views Hardware» more  DATE 2005»
15 years 10 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
15 years 10 months ago
Optimized Generation of Data-Path from C Codes for FPGAs
Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A....
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
15 years 10 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...