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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
15 years 9 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
101
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ISSS
2002
IEEE
109views Hardware» more  ISSS 2002»
15 years 9 months ago
The Formal Execution Semantics of SpecC
Rainer Dömer, Andreas Gerstlauer, Wolfgang M&...
ISSS
2002
IEEE
117views Hardware» more  ISSS 2002»
15 years 9 months ago
CMP on SoC: Architect's View
Shuichi Sakai