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RTCSA
2007
IEEE
15 years 6 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
ITNG
2007
IEEE
15 years 6 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
IESS
2007
Springer
156views Hardware» more  IESS 2007»
15 years 6 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
CCECE
2006
IEEE
15 years 6 months ago
A Survey of Secure B2C Commerce for Multicast Services
Services such as audio/video streaming, advertising, and software distribution can be delivered much more efficiently by Network Service Providers if multicast data distribution i...
Anil Kumar Venkataiahgari, J. William Atwood, Mour...
DATE
2006
IEEE
154views Hardware» more  DATE 2006»
15 years 6 months ago
An integrated open framework for heterogeneous MPSoC design space exploration
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
Federico Angiolini, Jianjiang Ceng, Rainer Leupers...