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» CAD Directions for High Performance Asynchronous Circuits
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ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
15 years 3 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
14 years 9 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
IPPS
2010
IEEE
14 years 7 months ago
Tile QR factorization with parallel panel processing for multicore architectures
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
Bilel Hadri, Hatem Ltaief, Emmanuel Agullo, Jack D...
ISCAS
2003
IEEE
189views Hardware» more  ISCAS 2003»
15 years 2 months ago
Bio-inspired optical flow circuits for the visual guidance of micro air vehicles
In 1986, Franceschini et al. built an optronic velocity sensor [11], the principle of which was based on the findings they had recently made on fly EMDs by performing electrophysio...
Franck Ruffier, Stéphane Viollet, S. Amic, ...
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
15 years 6 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...