Sciweavers

99 search results - page 15 / 20
» CAD Directions for High Performance Asynchronous Circuits
Sort
View
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
15 years 6 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
ICES
2005
Springer
177views Hardware» more  ICES 2005»
15 years 3 months ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
MOBIHOC
2007
ACM
15 years 9 months ago
On exploiting asymmetric wireless links via one-way estimation
A substantial percentage of links in wireless networks, especially low-power ones, is asymmetric. For the low-quality direction of asymmetric links, we observe based on testbed ex...
Lifeng Sang, Anish Arora, Hongwei Zhang
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 2 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
TACAS
2010
Springer
210views Algorithms» more  TACAS 2010»
15 years 4 months ago
Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors
Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratchpad” memories. The price for increase...
Alastair F. Donaldson, Daniel Kroening, Philipp R&...