99 search results - page 9 / 20 » CAD Directions for High Performance Asynchronous Circuits |
88
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
HIPC
2004
Springer
15 years 3 months ago
2004
Springer
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
A circuit and an associated lightweight protocol have been developed to secure communication between a control console and remote programmable network devices1 . The circuit provi...
ICCAD
1993
IEEE
15 years 1 months ago
1993
IEEE
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...