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» CHIPS: Custom Hardware Instruction Processor Synthesis
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89
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ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
15 years 6 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
DAC
2004
ACM
15 years 3 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
81
Voted
DDECS
2006
IEEE
108views Hardware» more  DDECS 2006»
15 years 3 months ago
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
ICPADS
1998
IEEE
15 years 1 months ago
A Dualthreaded Java Processor for Java Multithreading
Java-Web Computing paradigm changed Internet into computing environment. For Java-Web Computing and many Java applications, a new Java processor, called simultaneous multithreaded...
Chun-Mok Chung, Shin-Dug Kim
ISPASS
2006
IEEE
15 years 3 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...