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» CHIPS: Custom Hardware Instruction Processor Synthesis
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DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 3 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
ARC
2009
Springer
181views Hardware» more  ARC 2009»
15 years 4 months ago
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
Abstract. In this paper, we present CCProc, a flexible cryptography coprocessor for symmetric-key algorithms. Based on an extensive analysis of many symmetric-key ciphers, includi...
Dimitris Theodoropoulos, Alexandros Siskos, Dionis...
IEEEPACT
2006
IEEE
15 years 3 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
15 years 1 months ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 2 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...