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» CHIPS: Custom Hardware Instruction Processor Synthesis
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DATE
2003
IEEE
101views Hardware» more  DATE 2003»
15 years 3 months ago
Energy Estimation for Extensible Processors
This paper presents an efficient methodology for estimating the energy consumption of application programs running on extensible processors. Extensible processors, which are incr...
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj...
ICCAD
2005
IEEE
141views Hardware» more  ICCAD 2005»
15 years 6 months ago
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
Jason Cong, Guoling Han, Zhiru Zhang
ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
15 years 3 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 1 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
CODES
2002
IEEE
15 years 2 months ago
Compiler-directed customization of ASIP cores
This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft c...
T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua