267 search results - page 23 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
PAIRING
2007
Springer
15 years 3 months ago
2007
Springer
A series of recent algorithmic advances has delivered highly effective methods for pairing evaluation and parameter generation. However, the resulting multitude of options means m...
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...