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» CHIPS: Custom Hardware Instruction Processor Synthesis
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COMPSEC
2008
116views more  COMPSEC 2008»
14 years 9 months ago
Enforcing memory policy specifications in reconfigurable hardware
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reco...
Ted Huffmire, Timothy Sherwood, Ryan Kastner, Timo...
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
15 years 4 months ago
A future of customizable processors: are we there yet?
Customizable processors are being used increasingly often in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and p...
Laura Pozzi, Pierre G. Paulin
IEEEPACT
2006
IEEE
15 years 3 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
IEEEPACT
2006
IEEE
15 years 3 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
15 years 2 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...