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» CHIPS: Custom Hardware Instruction Processor Synthesis
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MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
15 years 3 months ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...
ERSA
2004
129views Hardware» more  ERSA 2004»
14 years 11 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
15 years 6 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
ESORICS
2006
Springer
15 years 1 months ago
Policy-Driven Memory Protection for Reconfigurable Hardware
Abstract. While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable har...
Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ry...
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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 3 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...