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» CHIPS: Custom Hardware Instruction Processor Synthesis
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DATE
2008
IEEE
107views Hardware» more  DATE 2008»
15 years 4 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 3 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
CODES
2007
IEEE
15 years 4 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
ICCAD
2004
IEEE
64views Hardware» more  ICCAD 2004»
15 years 6 months ago
Simultaneous design and placement of multiplexed chemical processing systems on microchips
Microchip structures represent an attractive platform for microscale chemical processing of fluidic systems. However, standardized design methods for these devices have not yet b...
Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan
HOTI
2002
IEEE
15 years 2 months ago
Architecture and Hardware for Scheduling Gigabit Packet Streams
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...