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» CHIPS: Custom Hardware Instruction Processor Synthesis
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IEEEPACT
2008
IEEE
15 years 4 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...
DSN
2008
IEEE
14 years 11 months ago
Detouring: Translating software to circumvent hard faults in simple cores
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
Albert Meixner, Daniel J. Sorin
CASES
2005
ACM
14 years 11 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
FDL
2003
IEEE
15 years 3 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
ICS
2009
Tsinghua U.
15 years 4 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell