267 search results - page 37 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
DDECS
2009
IEEE
15 years 1 months ago
2009
IEEE
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-o...
100
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
75
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ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
111
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FPL
2010
Springer
14 years 7 months ago
2010
Springer
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...