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» CHIPS: Custom Hardware Instruction Processor Synthesis
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GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS ad...
Chichyang Chen, Paul Chow
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 2 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ICS
2001
Tsinghua U.
15 years 2 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
FPL
2007
Springer
94views Hardware» more  FPL 2007»
15 years 3 months ago
An OCM based shared Memory controller for Virtex 4
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
Bas Breijer, Filipa Duarte, Stephan Wong
86
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ICASSP
2009
IEEE
14 years 7 months ago
VLSI for 5000-word continuous speech recognition
We have developed a VLSI chip for 5,000 word speakerindependent continuous speech recognition. This chip employs a context-dependent HMM (hidden Markov model) based speech recogni...
Young-kyu Choi, Kisun You, Jungwook Choi, Wonyong ...