267 search results - page 40 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
CODES
2006
IEEE
14 years 11 months ago
2006
IEEE
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
146
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DATE
2011
IEEE
14 years 1 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
70
Voted
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
82
Voted
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
100
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TCAD
2008
14 years 9 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...