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» CHIPS: Custom Hardware Instruction Processor Synthesis
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MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
15 years 4 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
CODES
2005
IEEE
15 years 3 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
HPCC
2007
Springer
15 years 3 months ago
FROCM: A Fair and Low-Overhead Method in SMT Processor
Simultaneous Multithreading (SMT)[1][2] and chip multiprocessors (CMP) processors [3] have emerged as the mainstream computing platform in major market segments, including PC, serv...
Shuming Chen, Pengyong Ma
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 2 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
15 years 3 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...