267 search results - page 46 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
74
Voted
EUROPAR
2009
Springer
15 years 4 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
IISWC
2009
IEEE
15 years 4 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
103
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ARC
2012
Springer
13 years 5 months ago
2012
Springer
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
SIGGRAPH
1993
ACM
15 years 1 months ago
1993
ACM
A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bi...