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» CHIPS: Custom Hardware Instruction Processor Synthesis
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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
13 years 11 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
14 years 29 days ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
DAC
1992
ACM
13 years 10 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
ARC
2006
Springer
88views Hardware» more  ARC 2006»
13 years 10 months ago
Integrating Custom Instruction Specifications into C Development Processes
Abstract. We describe a new approach for creating hardware description language (HDL) specifications for custom instructions, to form part of the instruction-set architecture (ISA)...
Jack Whitham, Neil C. Audsley
ASPDAC
2004
ACM
83views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Instruction set and functional unit synthesis for SIMD processor cores
—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, t...
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka,...