267 search results - page 5 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
DAGSTUHL
2004
14 years 11 months ago
2004
The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and c...
ASAP
2008
IEEE
14 years 11 months ago
2008
IEEE
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
ICCAD
1993
IEEE
1993
IEEE
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
15 years 1 months ago
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
FPL
2009
Springer
15 years 1 months ago
2009
Springer
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
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FPL
2006
Springer
15 years 1 months ago
2006
Springer
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...