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» CHIPS: Custom Hardware Instruction Processor Synthesis
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ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
15 years 1 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
SAMOS
2009
Springer
15 years 4 months ago
Runtime Adaptive Extensible Embedded Processors - A Survey
Current generation embedded applications demand the computation engine to offer high performance similar to custom hardware circuits while preserving the flexibility of software s...
Huynh Phung Huynh, Tulika Mitra
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
15 years 6 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
DSD
2002
IEEE
102views Hardware» more  DSD 2002»
15 years 2 months ago
Formal Verification of a DSP Chip Using an Iterative Approach
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
Ali Habibi, Sofiène Tahar, Adel Ghazel
VLSI
2007
Springer
15 years 3 months ago
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...
Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Za...