56 search results - page 10 / 12 » CMOS Current-controlled Oscillators |
117
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was present...
106
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
119
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ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
113
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper introduces a novel low-power digital future, are expected to run at frequencies beyond 10 MHz. In controller for high frequency dc-dc switch-mode power supplies addition...
125
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...