8 search results - page 2 / 2 » CMOS Leakage and Glitch Minimization for Power-Performance T... |
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DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
116
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GLVLSI
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
90
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ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...