Sciweavers

63 search results - page 6 / 13
» CMOS gate modeling based on equivalent inverter
Sort
View
69
Voted
ICONIP
2007
14 years 11 months ago
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually co...
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asa...
85
Voted
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 1 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...
90
Voted
TVLSI
2002
93views more  TVLSI 2002»
14 years 9 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
64
Voted
ASPDAC
2006
ACM
88views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
— A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impe...
Daisuke Kosaka, Makoto Nagata
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
15 years 1 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...