63 search results - page 7 / 13 » CMOS gate modeling based on equivalent inverter |
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
83
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
MJ
2007
14 years 9 months ago
2007
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wi...