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CODES
2003
IEEE
15 years 3 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
CODES
2003
IEEE
15 years 3 months ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
HICSS
2003
IEEE
186views Biometrics» more  HICSS 2003»
15 years 3 months ago
Personalization through Mask Marketing
Customized marketing, so called 1-to-1 marketing, is often viewed as the panacea of e-commerce. User profiles, such as click streams logging every site the user accesses, are expl...
Moritz Strasser, Alf Zugenmaier
ICPP
2003
IEEE
15 years 3 months ago
Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers
A hardware-assisted design, dubbed cache-oriented multistage structure (COMS), is proposed for fast packet forwarding. COMS incorporates small on-chip cache memory in its constitu...
Nian-Feng Tzeng
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