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ICCD
2003
IEEE
112views Hardware» more  ICCD 2003»
15 years 6 months ago
Power Efficient Data Cache Designs
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
Jaume Abella, Antonio González
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
14 years 7 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
15 years 1 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
FPL
2008
Springer
119views Hardware» more  FPL 2008»
14 years 11 months ago
Polymorphic wavelet architectures using reconfigurable hardware
Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Po...
Amit Pande, Joseph Zambreno
82
Voted
VLSID
2002
IEEE
126views VLSI» more  VLSID 2002»
15 years 10 months ago
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
Debashis Panigrahi, Clark N. Taylor, Sujit Dey