Sciweavers

869 search results - page 129 / 174
» Cache Architectures for Reconfigurable Hardware
Sort
View
118
Voted
IPPS
1994
IEEE
15 years 7 months ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao
155
Voted
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
16 years 13 days ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
124
Voted
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
16 years 12 days ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
126
Voted
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 7 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
127
Voted
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
15 years 9 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...