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FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
15 years 1 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
63
Voted
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
15 years 6 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
DATE
2005
IEEE
84views Hardware» more  DATE 2005»
15 years 3 months ago
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Mirko Loghi, Paolo Azzoni, Massimo Poncino
ISCA
2003
IEEE
124views Hardware» more  ISCA 2003»
15 years 2 months ago
A Highly-Configurable Cache Architecture for Embedded Systems
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
68
Voted
DATE
2004
IEEE
106views Hardware» more  DATE 2004»
15 years 1 months ago
A Self-Tuning Cache Architecture for Embedded Systems
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky