869 search results - page 27 / 174 » Cache Architectures for Reconfigurable Hardware |
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
ERSA
2009
14 years 7 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
ARC
2007
Springer
15 years 1 months ago
2007
Springer
Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common fun...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
