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» Cache Architectures for Reconfigurable Hardware
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DATE
2004
IEEE
151views Hardware» more  DATE 2004»
15 years 1 months ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
PDPTA
2000
14 years 11 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...
ANSS
2004
IEEE
15 years 1 months ago
Cache Simulation Based on Runtime Instrumentation for OpenMP Applications
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
Jie Tao, Josef Weidendorfer
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
14 years 7 months ago
A Reconfigurable Architecture for Secure Multimedia Delivery
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
Amit Pande, Joseph Zambreno
78
Voted
ICCAD
1998
IEEE
109views Hardware» more  ICCAD 1998»
15 years 1 months ago
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this featu...
Robert P. Dick, Niraj K. Jha