869 search results - page 32 / 174 » Cache Architectures for Reconfigurable Hardware |
80
Voted
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
Replacing functional units of an extensible processor with reconfigurable functional units enhances performance and flexibility of processors to execute custom instructions. That ...