869 search results - page 33 / 174 » Cache Architectures for Reconfigurable Hardware |
80
Voted
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
88
Voted
AHS
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
ASPDAC
2004
ACM
15 years 1 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hyb...