869 search results - page 45 / 174 » Cache Architectures for Reconfigurable Hardware |
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
ISCA
2007
IEEE
14 years 9 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper addresses the implementation of ReedSolomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB...
FCCM
2009
IEEE
15 years 4 months ago
2009
IEEE
—Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources....