869 search results - page 46 / 174 » Cache Architectures for Reconfigurable Hardware |
ERSA
2008
14 years 11 months ago
2008
This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning al...
ASAP
2007
IEEE
15 years 1 months ago
2007
IEEE
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
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ISLPED
1997
ACM
15 years 1 months ago
1997
ACM
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run tim...
ISMVL
2000
IEEE
15 years 2 months ago
2000
IEEE
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments o...