869 search results - page 51 / 174 » Cache Architectures for Reconfigurable Hardware |
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
CODES
2002
IEEE
15 years 2 months ago
2002
IEEE
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
104
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MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
AHS
2007
IEEE
15 years 1 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...