869 search results - page 54 / 174 » Cache Architectures for Reconfigurable Hardware |
ARC
2009
Springer
15 years 4 months ago
2009
Springer
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
103
click to vote
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software p...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
Motion estimation is a complex computation found in video compression algorithms, such as standards like MPEG-4 and H.263. This paper proposes an embedded reconfigurable array for...