869 search results - page 55 / 174 » Cache Architectures for Reconfigurable Hardware |
MICRO
1999
IEEE
15 years 2 months ago
1999
IEEE
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
ARC
2006
Springer
15 years 1 months ago
2006
Springer
We explore the application of Small-Scale Reconfigurability (SSR) to graphics hardware. SSR is an architectural technique wherein functionality common to multiple subunits is reuse...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
SBACPAD
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...