869 search results - page 56 / 174 » Cache Architectures for Reconfigurable Hardware |
128
Voted
ARC
2007
Springer
15 years 7 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
107
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CF
2006
ACM
15 years 9 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
127
Voted
IPPS
2008
IEEE
15 years 10 months ago
2008
IEEE
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
156
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HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
127
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...