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HICSS
1994
IEEE
152views Biometrics» more  HICSS 1994»
15 years 1 months ago
Simple COMA Node Implementations
Shared memory architectures often have caches to reduce the number of slow remote memory accesses. The largest possible caches exist in shared memory architectures called Cache-On...
Erik Hagersten, Ashley Saulsbury, Anders Landin
ERSA
2007
194views Hardware» more  ERSA 2007»
14 years 11 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 2 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
FPL
2006
Springer
113views Hardware» more  FPL 2006»
15 years 1 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 2 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...