869 search results - page 62 / 174 » Cache Architectures for Reconfigurable Hardware |
DATE
1997
IEEE
15 years 2 months ago
1997
IEEE
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
ASAP
2008
IEEE
15 years 4 months ago
2008
IEEE
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
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SBACPAD
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...