869 search results - page 62 / 174 » Cache Architectures for Reconfigurable Hardware |
100
click to vote
DATE
1997
IEEE
15 years 7 months ago
1997
IEEE
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
134
Voted
DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
149
Voted
ASAP
2008
IEEE
15 years 10 months ago
2008
IEEE
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
140
click to vote
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
150
Voted
SBACPAD
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...