869 search results - page 64 / 174 » Cache Architectures for Reconfigurable Hardware |
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
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SIPEW
2009
Springer
15 years 2 months ago
2009
Springer
Abstract. The excellent performance of the contemporary x86 processors is partially due to the complexity of their memory architecture, which therefore plays a role in performance ...
IPPS
1999
IEEE
15 years 2 months ago
1999
IEEE
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
VTS
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
PARELEC
2000
IEEE
15 years 2 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...