869 search results - page 68 / 174 » Cache Architectures for Reconfigurable Hardware |
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...
FCCM
2003
IEEE
15 years 3 months ago
2003
IEEE
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
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ECOOP
1995
Springer
15 years 1 months ago
1995
Springer
Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve p...
EUROPAR
2007
Springer
15 years 4 months ago
2007
Springer
Abstract. Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yiel...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...