869 search results - page 6 / 174 » Cache Architectures for Reconfigurable Hardware |
CHES
2008
Springer
14 years 11 months ago
2008
Springer
Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
101
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WMPI
2004
ACM
15 years 3 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
115
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SBCCI
2003
ACM
15 years 2 months ago
2003
ACM
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...